Lattice Boosts BFW III Products With SuperWIDE Family

ispMACH(TM) 5000B ISP(TM) CPLD Enhances Lattice's SuperWIDE(TM) Product Line With Improved Performance, sysIO(TM) and 2.5 Volt Support

HILLSBORO, Ore.--(BUSINESS WIRE)--June 3, 2002-- Lattice Semiconductor Corporation (Nasdaq:LSCC - News), the inventor of in-system programmable (ISP) logic products, today announced the release of the first member of its 2.5 Volt ispMACH 5000B family, the 256 macrocell ispMACH 5256B.

The introduction of this family continues Lattice's rollout of its 3rd generation BFW (Big-Fast-Wide) Complex PLD products. The ispMACH 5256B device is the first of four ispMACH 5000B devices which span logic capacities from 128 to 512 macrocells and offer performance as fast as 3.5ns tPD (pin-to-pin logic delay) and operating frequencies to 275MHz for the fastest family members.

Advanced process technology enables the ispMACH 5000B to provide high-speed performance and 2.5V power supply operation. Programmable sysIO interface capability provides flexible advanced I/O standard (GTL+, HSTL, SSTL, etc.) support. For the ispMACH 5256B, pin-to-pin delays (tPD) as fast as 4.0ns and operating frequencies (fMAX) up to 250 MHz are supported. SuperWIDE (68-input, 32-macrocell) logic blocks efficiently implement wide logic functions such as those found in advanced 32- and 64-bit systems.

The ispMACH 5000B family provides logic designers with a single architecture to meet a broad range of system requirements. The family includes multiple logic densities (128, 256, 384, and 512 macrocells) in a variety of advanced package and I/O options. The wide range of sysIO-capable pins (from 92 to 256 per device) provided in the ispMACH 5000B devices makes them ideal for wide bus interface and memory interface applications. The instant power-up capability of these devices makes them suitable for critical power-up sequence control in complex systems.

"The ispMACH 5000B family leverages the popular 5000 series SuperWIDE CPLD architecture and delivers a high performance, 2.5V solution that supports the advanced I/O interface standards required for today's complex system designs," said Steve Stark, Director of Product Marketing at Lattice.

sysIO Capability for Board-Level Performance

Each I/O pin on the ispMACH 5000B devices can be configured to support high-speed memory interfaces, advanced bus standards, or general-purpose interfaces. General-purpose interface support includes LVTTL or LVCMOS (3.3, 2.5 or 1.8 Volts). Programmable drive levels for these standards facilitate the elimination of series termination resistors, further reducing overall system cost.

Interface to high speed DRAMs, SRAMs, and other high performance memory devices is made possible with SSTL2, SSTL3, and HSTL I/O support. The ispMACH 5000B family also supports GTL+ and PCI I/O configurations for use in high-speed bus interfaces.

SuperWIDE Logic Blocks for High Performance

The new family uses Lattice's industry-leading SuperWIDE 68-input logic block employed in earlier 3.3 Volt ispLSI® 5000VE and ispMACH 5000VG families. The SuperWIDE architecture, the widest available in any CPLD, provides excellent support for next-generation 64-bit applications. This SuperWIDE capability can deliver a 60% performance gain for complex logic functions when compared to traditional CPLD devices using 36-input logic blocks.

Design Tools

The ispMACH 5000B family is supported by Lattice's new ispLEVER(TM) design tools available now. The ispLEVER tools, Lattice's platform for next-generation logic design, provide designers with rapid access to the performance and features of the ispMACH 5000B devices while maximizing resource utilization. This is achieved through timing driven placement & routing coupled with optimized synthesis support from vendors such as Mentor Graphics® and Synplicity®. Additional third-party EDA tool support is provided through industry standard EDIF netlist import and export. The ispLEVER software is available in PC as well as UNIX workstation versions.

The ispLEVER design tools, including Synplicity's Synplify® VHDL and Verilog synthesis tools, are available for download from the Lattice web site. These full-featured tools are designed to provide users easy access to the innovation and high performance of the ispMACH 5000B family architecture.

Price and Availability

The ispMACH 5256B is available now in 128-pin TQFP, 208-pin PQFP and 256-ball fine pitch BGA (fpBGA) packages. The fpBGA package features a space-saving 1-millimeter solder ball pitch. The ispMACH 5000B family also supports system designers' needs for density migration within a common package/pinout footprint. As a result, designers are able to shrink or expand their designs across multiple logic macrocell density options while maintaining the same printed circuit board layout. The balance of the ispMACH 5000B devices are expected to be released in the third quarter of 2002. Projected pricing for the ispMACH 5256B is as low as $8.00 in high-volume.

About Lattice Semiconductor

Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of high-performance ISP(TM) programmable logic devices (PLDs), Field Programmable Gate Arrays (FPGAs) and Field Programmable System Chip (FPSC) devices. Lattice offers total solutions for today's system designs by delivering the most innovative programmable silicon products that embody leading-edge system expertise.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communication, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503/268-8000, FAX 503/268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com.

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

Lattice Semiconductor Corporation, L (& design), Lattice (& design), in-system programmable, ispLEVER, SuperWIDE, ispMACH, ispLSI, sysIO, ISP and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

EDITORS NOTE: the "PD" in tPD and "MAX" in fMAX should appear as subscript.

     Lattice Semiconductor Corp.
     Steve Stark, 503/268-8386
     Steve.Stark@latticesemi.com